An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles

1. Introduction: As digital Integrated Circuits (ICs) are driven at higher and higher clock frequencies, the need for a better clock net routing scheme has become essential. For complex ASICs (or VLSI), circuit designers ensure proper timing by carefully planning and implementing the distribution of clocks throughout the circuit. This part of the design process is critical because poor clock distribution can cause a circuit to malfunction, especially because of problems caused by skew and latency. To minimize skew and latency, circuit designers create clock trees that balance delays and loads in the clock buffers. There is less room for error when the clock period becomes small, so great care must be taken to deliver the clock pulse to all points. A planar clock tree may be implemented on a single metal layer. A clock net on the metal layer with the smallest RC delay is preferable since it avoids the use of vias in the clock net and makes the layout more tolerant of process variations. Furthermore, it is easier to adjust a planar clock tree for zero skew and minimal phase delay [ZD 96]. However, it is not simple to achieve uniform electrical parameters on multiple layers since connections between the various layers are made by plated-through holes and vias. This motivates our research on planar clock routing. A pla-nar clock routing has traces in either the horizontal or vertical direction for ease of design and manufacture, and reduces the delay and attenuation through vias as well as the sensitivity to process variation.